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apds-9130 digital proximity sensor data sheet description the apds-9130 provides ir led and a complete proximity detection system in a single 8 pin package. the proximity function ofers plug and play detection to 100 mm (without front glass) thus eliminating the need for factory calibration of the end equipment or sub-assembly. the proximity detection feature operates well from bright sunlight to dark rooms. the wide dynamic range also allows for operation in short distance detection behind dark glass such as a cell phone. the proximity function is targeted specifcally towards near feld proximity applications. in cell phones, the proximity detection can detect when the user positions the phone close to their ear. the device is fast enough to provide proximity information at a high repetition rate needed when answering a phone call. this provides both improved green power saving capability and the added security to lock the computer when the user is not present. the addition of the micro-optics lenses within the module, provide highly efcient transmission and reception of infrared energy which lowers overall power dissipation. ordering information part number packaging quantity apds-9130 tape & reel 2500 per reel APDS-9130-140 tape & reel 1000 per reel apds-9130-200 tape & reel 1000 per reel features ir led and proximity detector in an optical module ? proximity detection C fully calibrated to 100 mm detection C integrated ir led and synchronous led driver C eliminates factory calibration of prox ? programmable wait timer C wait state power C 90 a typical C programmable from 2.7 ms to > 8 sec ? i 2 c interface compatible C up to 400 khz (i 2 c fast-mode) C dedicated interrupt pin ? sleep mode power - 2.2 a typical ? small package l3.94 x w2.36 x h1.35 mm applications ? cell phone touch-screen disable ? notebook/monitor security ? automatic speakerphone enable ? automatic menu pop-up ? digital camera eye sensor package diagram 7 - scl 6 - gnd 5 - led a 8 - vdd 1 - sda 2 - int 3 - ldr 4 - led k
2 functional block diagram detailed description the apds-9130 device provides on-chip ch1 diode, inte - grating amplifers, adcs, accumulators, clocks, bufers, comparators, a state machine and an i 2 c interface. each device has one ch1 infrared-responding (ir) photodiode. communication to the device is accomplished through a fast (up to 400 khz), two-wire i 2 c serial bus for easy con - nection to a microcontroller or embedded controller. the digital output of the apds-9130 device is inherently more immune to noise when compared to an analog interface. the apds-9130 provides a separate pin for level-style interrupts. when interrupts are enabled and a pre-set value is exceeded, the interrupt pin is asserted and remains asserted until cleared by the controlling frmware. the interrupt feature simplifes and improves system efciency by eliminating the need to poll a sensor for a proximity value. an interrupt is generated when the value of proximity conversion exceeds either an upper or lower threshold. additionally, a programmable interrupt per - sistence feature allows the user to determine how many consecutive exceeded thresholds are necessary to trigger an interrupt. interrupt thresholds and persistence settings are confgured independently for proximity. proximity detection is fully provided with an 850 nm ir led. an internal led driver (ldr) pin, is jumper connected to the led cathode (led k) to provide a factory calibrated proximity of 100 +/- 20 mm. this is accomplished with a proprietary current calibration technique that accounts for all variances in silicon, optics, package and most impor - tantly ir led output power. this will eliminate or greatly reduce the need for factory calibration that is required for most discrete proximity sensor solutions. while the apds-9130 is factory calibrated at a given pulse count, the number of proximity led pulses can be programmed from 1 to 255 pulses, which will allow greater proximity distances to be achieved. each pulse has a 16 s period. upper threshold lower threshold interrupt i 2 c interface control logic prox detect adc data int scl sda vdd gnd ldr led k led a prox ir led ch1 led regulated constant current sink
3 i/o pins confguration pin name type description 1 sda i/o i 2 c serial data i/o terminal C serial data i/o for i 2 c. 2 int o interrupt C open drain. 3 ldr i led driver for proximity emitter C up to 100 ma, open drain. 4 ledk o led cathode, connect to ldr pin in most systems to use internal led driver circuit 5 leda i led anode, connect to v bat t on pcb 6 gnd power supply ground. all voltages are referenced to gnd. 7 scl i i 2 c serial clock input terminal C clock signal for i 2 c serial data. 8 v dd power supply voltage. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? parameter symbol min max units test conditions power supply voltage v dd 3.8 v [1] digital voltage range -0.5 3.8 v digital output current i o -1 20 ma storage temperature range tstg -40 85 c ? stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may afect device reliability. note: 1. all voltages are with respect to gnd. recommended operating conditions parameter symbol min typ max units operating ambient temperature t a -30 85 c supply voltage v dd 2.2 3.0 3.6 v supply voltage accuracy, v dd total error including transients -3 +3 % led supply voltage v bat t 2.5 4.5 v
4 operating characteristics, v dd = 3 v, t a = 25 c (unless otherwise noted) parameter symbol min typ max units test conditions supply current [1] i dd 195 250 a active 90 wait mode 2.2 4.0 sleep mode int sda output low voltage v ol 0 0.4 v 3 ma sink current 0 0.6 6 ma sink current leakage current, sda, scl, int pins i leak -5 5 a leakage current, ldr pin i leak -10 10 a scl, sda input high voltage v ih 1.25 vdd v scl, sda input low voltage v il 0.54 v note: 1. the power consumption is raised by the programmed amount of proximity led drive during the 8 us the led pulse is on. the nominal and maximum values are shown under proximity characteristics. there the i dd supply current is i dd active + proximity led drive programmed value. proximity characteristics, v dd = 3 v, t a = 25 c, pgain = 1, pen = 1 (unless otherwise noted) parameter min typ max units test conditions i dd supply current C ldr pulse on 3 ma adc conversion time step size 2.58 2.73 2.9 ms ptime = 0xf adc number of integration steps 1 steps ptime = 0xf full scale adc counts 1023 counts ptime = 0xf proximity ir led pulse count 0 255 pulses proximity pulse period 16.0 s proximity pulse C led on time 7.3 s proximity led drive 100 ma pdrive = 0 i sink sink current @ 600 mv, ldr pin 50 pdrive = 1 25 pdrive = 2 12.5 pdrive = 3 proximity adc count value, no object 100 200 counts dedicated power supply vbatt = 3 v led driving 8 pulses, pdrive = 00, pgain = 10, open view (no glass) and no refective object above the module. [1] proximity adc count value, 100 mm distance object 450 520 590 counts refecting object C 73 mm x 83 mm kodak 90% grey card, 100 mm distance, led driving 8 pulses, pdrive = 00, pgain = 10, open view (no glass) above the module. tested value is the average of 5 consecutive readings. [1] note: 1. 100 ma and 8 pulses are the recommended driving conditions. for other driving conditions, contact avago field sales.
5 ir led characteristics, v dd = 3 v, t a = 25 c (unless otherwise noted) parameter min typ max units test conditions peak wavelength, p 850 nm i f = 20 ma spectrum width, half power, ? 40 nm i f = 20 ma optical rise time, t r 20 ns i f = 100 ma optical fall time, t f 20 ns i f = 100 ma wait characteristics, v dd = 3 v, t a = 25 c, wen = 1 (unless otherwise noted) parameter min typ max units test conditions wait step size 2.27 2.4 2.56 ms w time = 0ff ac electrical characteristics, v dd = 3 v, t a = 25 c (unless otherwise noted) * parameter symbol min. max. unit clock frequency (i 2 c-bus only) f scl 0 400 khz bus free time between a stop and start condition t buf 1.3 C s hold time (repeated) start condition. after this period, the frst clock pulse is generated t hdsta 0.6 C s set-up time for a repeated start condition t su;sta 0.6 C s set-up time for stop condition t su;sto 0.6 C s data hold time t hd;dat 0 C ns data set-up time t su;dat 100 C ns low period of the scl clock t low 1.3 C s high period of the scl clock t high 0.6 C s clock/data fall time t f 20 300 ns clock/data rise time t r 20 300 ns input pin capacitance c i C 10 pf * specifed by design and characterization; not production tested. figure 1. timing diagrams start condition stop condition p sda t t hd;dat t buf v ih v il scl t su;sta t high t f t r t hd;sta t low v ih v il s p s su;dat t su;sto
6 0 0.2 0.4 0.6 0.8 1 1.2 300 400 500 600 700 800 900 1000 1100 normalized responsitivity wavelength (nm) ch0 ch1 normalized idd @ 3 v 25 c 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 vdd (v) 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 -60 -40 -20 0 20 40 60 80 100 normalized idd @ 3v temperature (c) 0 0.2 0.4 0.6 0.8 1 1.2 - 50 - 40 - 30 - 20 - 10 0 10 20 30 40 50 normalized radiant intensity angle (deg) 0 0.2 0.4 0.6 0.8 1 1.2 - 80 - 60 - 40 - 20 0 20 40 60 80 normalized responsitivity angle (deg) figure 2. spectral response figure 3a. normalized idd vs. vdd figure 3b. normalized idd vs. temperature figure 4a. normalized pd responsitivity vs. angular displacement figure 4b. normalized led angular emitting profle
7 principles of operation system state machine an internal state machine provides system control of the proximity detection, and power management features of the device. at power up, an internal power-on-reset ini - tializes the device and puts it in a low-power sleep state. when a start condition is detected on the i2c bus, the device transitions to the idle state where it checks the enable register (0x00) pon bit. if pon is disabled, the device will return to the sleep state to save power. otherwise, the device will remain in the idle state until a proximity function is enabled. once enabled, the device will execute the prox and wait states in sequence as indicated in figure 5. upon completion and return to idle, the device will automatically begin a new prox?wait cycle as long as pon and pen remain enabled. if the prox function generates an interrupt and the sleep- after-interrupt (sai) feature is enabled, the device will transition to the sleep state and remain in a low-power mode until an i2c command is received. figure 5. simplifed state diagram !wen pen sleep idle w ait prox i 2 c start !pon int & sai wen !pen & wen
8 proximity detection ch1 prox integration prox control prox adc prox led current driver ch0 pdatah(r0x019) pdrive(r0x0f , b7:6) prox data ir led ptime(r0x02) pv alid(r0x13, b1) pdl(r0x0d,b0) ppulse(r0x0e) pgain(r0x0f , b3:2) poffset(r0x1e) psa t(r0x13, b6) pdiode(r0x0f , b5:4) background energy pdatal(r0x018) object ldr ledk leda led on ir led pulses background energy reected ir led + background energy 16.0 s 7.3 s led o proximity detection is accomplished by measuring the amount of ir energy, from the internal ir led, refected of an object to determine its distance. the internal proximity ir led is driven by the integrated proximity led current driver as shown in figure 6. the led current driver, output on the ldr terminal, provides a regulated current sink that eliminates the need for an external current limiting resistor. the combination of proximity led drive strength (pdrive) and proximity drive level (pdl) determine the drive current. pdrive sets the drive current to 100 ma, 50 ma, 25 ma, or 12.5 ma when pdl is not asserted. however, when pdl is asserted, the drive current is reduced by a factor of 9. referring to the detailed state machine fgure, the led current driver pulses the ir led as shown in figure 7 during the prox accum state. figure 7 also illustrates that the led on pulse has a fxed width of 7.3 s and period of 16.0 s. so, in addition to setting the proximity drive current, 1 to 255 proximity pulses (ppulse) can be programmed. when deciding on the number of proximity pulses, keep in mind that the signal increases proportionally to ppulse, while noise increases by the square root of ppulse. figure 6 illustrates light rays emitting from the internal ir led, refecting of an object, and being absorbed by the ch1 photodiodes. the proximity diode selector (pdiode) selects ch1 diode for a given proximity measurement. note that pdiode must be set for proximity detection to work. figure 6. proximity detection figure 7. proximity led current driver waveform referring again to figure 7, the refected ir led and the background energy is integrated during the led on time, then during the led of time, the integrated background energy is subtracted from the led on time energy, leaving the ir led energy to accumulate from pulse to pulse. the proximity gain (pgain) determines the integration rate, which can be programmed to 1, 2, 4, or 8 gain. at power up, pgain defaults to 1 gain, which is recom - mended for most applications. for reference, pgain equal to 4 is comparable to the apds-9900s 1 gain setting. during led on time integration, the proximity saturation bit in the status register (0x13) will be set if the integra - tor saturates. this condition can occur if the proximity gain is set too high for the lighting conditions, such as in the presence of bright sunlight. once asserted, psat will remain set until a special function proximity interrupt clear command is received from the host (see command register).
9 air gap, g plastic/glass window apds-9130 windows thickness, t figure 8. proximity detection figure 9a. ps output vs. distance at 100 ma, pgain = 10, at various pulse count. no glass in front of the module, 18% kodak grey card. figure 9b. ps output vs. distance at 100 ma, pgain = 10, at various pulse count. no glass in front of the module, 90% kodak grey card. 4p, 100 ma 6p,100 ma 8p, 100 ma 16p, 100 ma 4p, 100 ma 6p,100 ma 8p, 100 ma 16p, 100 ma 4p, 100 ma 6p,100 ma 8p, 100 ma 16p, 100 ma 0 100 200 300 400 500 600 700 800 900 1000 1100 0 2 4 6 8 10 12 14 16 ps count distance (cm) 0 100 200 300 400 500 600 700 800 900 1000 1100 0 2 4 6 8 10 12 14 16 ps count distance (cm) after the programmed number of proximity pulses have been generated, the proximity adc converts and scales the proximity measurement to a 16-bit value, then stores the result in two 8-bit proximity data (pdatax) registers. adc scaling is controlled by the proximity adc conver - sion time (ptime) which is programmable from 1 to 256 2.73-ms time units. however, depending on the applica - tion, scaling the proximity data will equally scale any ac - cumulated noise. therefore, in general, it is recommended to leave ptime at the default value of one 2.73 ms adc conversion time (0xff). in many practical proximity applications, a number of optical system and environmental conditions can produce an ofset in the proximity measurement result. to counter these efects, a proximity ofset (poffset) is provided which allows the proximity data to be shifted positive or negative. once the frst proximity cycle has completed, the proximity valid (pvalid) bit in the status register will be set and remain set until the proximity detection function is disabled (pen). optical design considerations the apds-9130 simplifes the optical system design by eliminating the need for light pipes and improves system optical efciency by providing apertures and package shielding which will reduce crosstalk when placed in the fnal system. by reducing the ir led to glass surface crosstalk, proximity performance is greatly improved and enables a wide range of cell phone applications utilizing the apds-9130. the module package design has been optimized for minimum package foot print and short distance proximity of 100 mm typical. the spacing between the glass surface and package top surface is critical to controlling the crosstalk. if the package to top surface spacing gap, window thickness and transmittance are met, there should be no need to add additional com - ponents (such as a barrier) between the led and photo - diode. thus with some simple mechanical design imple - mentations, the apds-9130 will perform well in the end equipment system. apds-9130 module optimized design parameters: ? window thickness, t 1.0 mm ? air gap, g 1.0 mm [1] ? assuming window ir transmittance 90% note: 1. applications with an air gap from 0.5 mm to 1.0 mm are recommended to use pofset register (0x1e) in their factory calibration. the apds-9130 is available in a low profle package that contains optics that provide optical gain on both the led and the sensor side of the package. the device has a package z height of 1.35 mm and will support an air gap of 1.0 mm between the glass and the package. the assumption of the optical system level design is that glass surface above the module is 1.0 mm. by integrating the micro-optics in the package, the ir energy emitted can be reduced thus conserving the precious battery life in the application. the system designer can optimize his designs for slim form factor z height as well as improve the proximity sensing, save battery power, and disable the touch screen in a cellular phone.
10 interrupts the interrupt feature simplifes and improves system ef - fciency by eliminating the need to poll the sensor for proximity values outside of a user-defned range. while the interrupt function is always enabled and its status is available in the status register (0x13), the output of the interrupt state can be enabled using the proximity interrupt enable (pien) felds in the enable register (0x00). four 16-bit interrupt threshold registers allow the user to set limits below and above a desired proximity range. an out-of-range proximity interrupt can be generated when the proximity data (pdata) falls below the proximity interrupt low threshold (piltx) or exceeds the proximity interrupt high threshold (pihtx). it is important to note that the thresholds are evaluated in sequence, frst the low threshold, then the high threshold. as a result, if the low threshold is set above the high threshold, the high threshold is ignored and only the low threshold is evaluated. to further control when an interrupt occurs, the device provides a persistence flter. the persistence flter allows the user to specify the number of consecutive out- of-range proximity occurrences before an interrupt is generated. the persistence flter register (0x0c) allows the user to set the proximity persistence flter (ppers) values. see the persistence flter register for details on the persis - tence flter values. once the persistence flter generates an interrupt, it will continue until a special function interrupt clear command is received (see command register). figure 10. programmable interrupt prox adc prox data prox integration ch1 upper limit lower limit prox persistence pil th(r09), pil tl(r08) pihth(r0x0b), pihtl(r0x0a) ppers(r0x0c, b7:4)
11 state diagram the system state machine shown in figure 5 provides an overview of the states and state transitions that provide system control of the device. this section highlights the programmable features, which afect the state machine cycle time, and provides details to determine system level timing. upon vdd power on, it is recommended to wait at least 4.5ms before issuing the i2c command. when the proximity detection feature is enabled (pen), the state machine transitions through the prox init, prox accum, prox wait, and prox adc states. the prox init and prox wait times are a fxed 2.73 ms, whereas the prox accum time is determined by the number of proximity led pulses (ppulse) and the prox adc time is determined by the integration time (ptime). the formulas to determine the prox accum and prox adc times are given in the as - sociated boxes in figure 11. if an interrupt is generated as a result of the proximity cycle, it will be asserted at the end of the prox adc state and transition to the sleep state if sai is enabled. when the power management feature is enabled (wen), the state machine will transition in turn to the wait state. the wait time is determined by wlong, which extends normal operation by 12 when asserted, and wtime. the formula to determine the wait time is given in the box as - sociated with the wait state in figure 11. figure 11. extended state diagram prox w ait sleep idle w ait prox init prox accum prox adc prox t ime: 2.73 ms ppulse: 0 ~ 255 pulses t ime: 16.0 s/pulse range: 0 ~ 4.1 ms t ime: 2.73 ms ptime: 1 ~ 256 steps t ime: 2.73 ms/step range: 2.73 ms ~ 699 ms wtime: 1 ~ 256 steps wlong = 0 wlong = 1 t ime: 2.73 ms/step range: 2.73 ms ~ 699 ms !wen & !pon i 2 c start wen !pen & wen note: pon, pen, wen, aen, and sai are elds in the enable register (0x00). pen int & sai 32.8 ms/step 32.8 ms ~ 8.39s
12 power management power consumption can be managed with the wait state, because the wait state typically consumes only 90 a of idd current. an example of the power management feature is given below. with the assumptions provided in the example, average idd is estimated to be 157 a. power management system state machine state programmable parameter programmed value duration typical current prox init 2.73 ms 0.195 ma prox accum ppulse 0x04 0.064 ms prox accum ? led on 0.029 ms (note 1) 103 ma prox accum ? led off 0.035 ms (note 2) 0.195 ma prox wait 2.73 ms 0.195 ma prox adc ptime 0xff 2.73 ms 0.195 ma wait wtime wlong 0xee 0 49.2 ms 0.090 ma notes: 1. prox accum ? led on time = 7.3 s per pulse 4 pulses = 29.3s = 0.029 ms 2. prox accum ? led of time = 8.7 s per pulse 4 pulses = 34.7s = 0.035 ms average idd current = ((0.029 103) + (0.035 x 0.195) + (2.73 0.195) + (49.2 0.195) + (2.73 0.195 2)) / 57 = 157 a keeping with the same programmed values as the example, the table below shows how the average idd current is afected by the wait state time, which is determined by wen, wtime, and wlong. note that the worst-case current occurs when the wait state is not enabled. average idd current wen wtime wlong wait state average idd current 0 n/a n/a 0 ms 557 a 1 0xff 0 2.73 ms 441 a 1 0xee 0 49.2 ms 157 a 1 0x00 0 699 ms 96 a 1 0x00 1 8389 ms 91 a
13 basic software operation the following pseudo-code shows how to do basic initialization of the apds-9130. uint8 pime, wtime, ppulse; wtime = 0xf; // 2.7 ms C minimum wait time ptime = 0xf; // 2.7 ms C minimum prox integration time ppulse = 1; // minimum prox pulse count writeregdata(0, 0); //disable and powerdown writeregdata (2, ptime); writeregdata (3, wtime); writeregdata (0xe, ppulse); uint8 pdrive, pdiode, pgain; pdrive = 0; //100ma of led power pdiode = 0x20; // ch1 diode pgain = 0; //1x prox gain writeregdata (0xf, pdrive | pdiode | pgain); uint8 wen, pen, pon; wen = 8; // enable wait pen = 4; // enable prox pon = 1; // enable power on writeregdata (0, wen | pen | pon); // writeregdata(0,0x0f ); wait(12); //wait for 12 ms int ch0_data, ch1_data, prox_data; ch0_data = read_word(0x14); ch1_data = read_word(0x16); prox_data = read_word(0x18); writeregdata(uint8 reg, uint8 data) { m_i2cbus.writei2c(0x39, 0x80 | reg, 1, &data); } uint16 read_word(uint8 reg); { uint8 barr[2]; m_i2cbus.readi2c(0x39, 0xa0 | reg, 2, ref barr); return (uint16)(barr[0] + 256 * barr[1]); }
14 i 2 c protocol interface and control of the apds-9130 is accomplished through an i 2 c serial compatible interface (standard or fast mode) to a set of registers that provide access to device control functions and output data. the device supports a single slave address of 0x39 hex using 7 bit addressing protocol. (contact factory for other addressing options.) the i 2 c standard provides for three types of bus trans - action: read, write and a combined protocol. during a write operation, the frst byte written is a command byte followed by data. in a combined protocol, the frst byte written is the command byte followed by reading a series of bytes. if a read command is issued, the register address from the previous command will be used for data access. likewise, if the msb of the command is not set, the device will write a series of bytes at the address stored in the last valid command with a register address. the command byte contains either control information or a 5 bit register address. the control commands can also be used to clear interrupts. for a complete description of i 2 c protocols, please review the i 2 c specifcation at: http://www.nxp. com start and stop conditions scl sda s p start condition stop condition data transfer on i 2 c-bus sda scl 1 7 2 8 acknowledgement signal from slave msb start or repeated start condition s or sr ack ack 9 sr or p 1 2 3 to 8 9 acknowledgement signal from receiver stop or repeated start condition sr p 1 2 3 to 8 9 ack msb msb a complete data transfer s 1 ? 7 8 9 1 ? 7 8 9 1 ? 7 8 9 p stop condition start condition data ack data ack r/w ack address sda scl
15 a acknowledge (0) n not acknowledged (1) p stop condition r read (1) s start condition sr repeated start condition w write (0) continuation of protocol master-to-slave slave-to-master 1 7 1 1 8 1 1 7 1 1 8 1 1 s slave address w a command code a sr slave address r a data n p i 2 c read protocol C combined format 1 7 1 1 8 1 8 1 1 s slave address w a command code a data a p i 2 c write protocol 1 7 1 1 8 1 1 s slave address w a command code a p i 2 c write protocol (clear interrupt) 1 7 1 1 8 1 8 1 8 1 1 s slave address w a command code a data low a data high a p i 2 c write word protocol 1 7 1 1 8 1 1 7 1 1 8 1 s slave address w a command code a sr slave address r a data low a 8 1 1 data high n p i 2 c read word protocol
16 register set the apds-9130 is controlled and monitored by data registers and a command register accessed through the serial interface. these registers provide for a variety of control functions and can be read to determine results of the adc conversions. address resister name r/w register function reset value ? command w specifes register address 0x00 0x00 enable r/w enable of states and interrupts 0x00 0x02 ptime r/w proximity adc time 0xff 0x03 wtime r/w wait time 0xff 0x08 piltl r/w proximity interrupt low threshold low byte 0x00 0x09 pilth r/w proximity interrupt low threshold hi byte 0x00 0x0a pihtl r/w proximity interrupt hi threshold low byte 0x00 0x0b pihth r/w proximity interrupt hi threshold hi byte 0x00 0x0c pers r/w interrupt persistence flters 0x00 0x0d config r/w confguration 0x00 0x0e ppulse r/w proximity pulse count 0x00 0x0f control r/w gain control register 0x00 0x12 id r device id id 0x13 status r device status 0x00 0x18 pdatal r proximity adc low data register 0x00 0x19 pdatah r proximity adc high data register 0x00 0x1e poffset r/w proximity ofset register - - the mechanics of accessing a specifc register depends on the specifc protocol used. see the section on i 2 c protocols on the previous pages. in general, the command register is written frst to specify the specifc control/status register for following read/write operations.
17 command register the command registers specifes the address of the target register for future write and read operations. 7 6 5 4 3 2 1 0 command cmd type add C field bits description command 7 select command register. must write as 1 when addressing command register. type 6:5 selects type of transaction to follow in subsequent data transfers: field value integration time 00 repeated byte protocol transaction 01 auto-increment protocol transaction 10 reserved C do not use 11 special function C see description below byte protocol will repeatedly read the same register with each data access. block protocol will provide auto-increment function to read successive bytes. add 4:0 address register/special function register. depending on the transaction type, see above, this feld either specifes a special function command or selects the specifc control-status-register for following write or read transactions: field value read value 00000 normal C no action 00101 proximity interrupt clear 00110 reserved - do not write 00111 proximity interrupt clear other reserved C do not write proximity interrupt clear. clears any pending proximity interrupt. this special function is self clearing. enable register (0x00) the enable register is used primarily to power the apds-9130 device on/of, enable functions, and interrupts. 7 6 5 4 3 2 1 0 address enable reserved sai pien reserved wen pen reserved pon 0x00 field bits description reserved 7 reserved. write as 0. sai 6 sleep after interrupt. when asserted, the device will power down at the end of a proximity cycle if an interrupt has been generated. pien 5 proximity interrupt mask. when asserted, permits proximity interrupts to be generated. reserved 4 reserved. write as 0 wen 3 wait enable. this bit activates the wait feature. writing a 1 activates the wait timer. writing a 0 disables the wait timer. pen 2 proximity enable. this bit activates the proximity function. writing a 1 enables proximity. writing a 0 disables proximity. reserved 1 reserved. write as 0 pon 0 power on. this bit activates the internal oscillator to permit the timers and adc channels to operate. writing a 1 activates the oscillator. writing a 0 disables the oscillator.
18 proximity time control register (0x02) the proximity timing register controls the integration time of the proximity adc in 2.73 ms increments. it is recommended that this register be programmed to a value of 0xf (1 cycle, 1023 bits). field bits description ptime 7:0 value cycles time max count 0xf 1 2.73 ms 1023 wait time register (0x03) wait time is set 2.73 ms increments unless the wlong bit is asserted in which case the wait times are 12x longer. wtime is programmed as a 2s complement number. field bits description wtime 7:0 register value wall time time (wlong = 0) time (wlong = 1) 0xf 1 2.73 ms 0.033 sec 0xb6 74 202 ms 2.4 sec 0x00 256 699 ms 8.4 sec note. the proximity wait time register should be confgured before pen and/or aen is/are asserted. proximity interrupt threshold register (0x08 ? 0x0b) the proximity interrupt threshold registers provide the values to be used as the high and low trigger points for the com - parison function for interrupt generation. if the value generated by proximity channel crosses below the lower threshold specifed, or above the higher threshold, an interrupt is signaled to the host processor. register address bits description piltl 0x08 7:0 proximity adc channel low threshold lower byte pilth 0x09 7:0 proximity adc channel low threshold upper byte pihtl 0x0a 7:0 proximity adc channel high threshold lower byte pihth 0x0b 7:0 proximity adc channel high threshold upper byte
19 persistence register (0x0c) the persistence register controls the fltering interrupt capabilities of the device. confgurable fltering is provided to allow interrupts to be generated after each adc integration cycle or if the adc integration has produced a result that is outside of the values specifed by threshold register for some specifed amount of time. 7 6 5 4 3 2 1 0 pers ppers reserved 0x0c field bits description ppers 7:4 proximity interrupt persistence. controls rate of proximity interrupt to the host processor. field value meaning interrupt persistence function 0000 every every proximity cycle generates an interrupt 0001 1 1 consecutive proximity values out of range 1111 15 15 consecutive proximity values out of range reserved. 3:0 reserved. write as 0 confguration register (0x0d) the confguration register sets the proximity led drive level and wait long time. 7 6 5 4 3 2 1 0 config reserved reserved wlong pdl 0x0d field bits description reserved 7:3 reserved. write as 0. reserved 2 reserved. write as 0. wlong 1 wait long. when asserted, the wait cycles are increased by a factor 12x from that programmed in the wtime register. pdl 0 proximity drive level. when asserted, the proximity ldr drive current is reduced by 9. proximity pulse count register (0x0e) the proximity pulse count register sets the number of proximity pulses that the ldr pin will generate during the prox accum state. the pulses are generated at a 62.5 khz rate. 100 ma and 8 pulses are the recommended driving conditions. for other driving conditions, contact avago field sales. 7 6 5 4 3 2 1 0 ppulse ppulse 0x0e field bits description ppulse 7:0 proximity pulse count. specifes the number of proximity pulses to be generated.
20 control register (0x0f) the control register provides eight bits of miscellaneous control to the analog block. these bits typically control functions such as gain settings and/or diode selection. 7 6 5 4 3 2 1 0 control pdrive pdiode pgain reserved 0x0f field bits description pdrive 7:6 led drive strength. field value led strength pdl = 0 led strength pdl = 1 00 100 ma 11.1 ma 01 50 ma 5.6 ma 10 25 ma 2.8 ma 11 12.5 ma 1.4 ma pdiode 5:4 proximity diode select. field value diode selection 00 reserved 01 reserved 10 proximity uses the ch1 diode 11 reserved pgain 3:2 proximity gain control. field value proximity gain value 00 1x gain 01 2x gain 10 4x gain 11 8x gain reserved 1:0 reserved. write as 0
21 device id register (0x12) the id register provides the value for the part number. the id register is a read-only register. 7 6 5 4 3 2 1 0 id device id 0x12 field bits description id 7:0 part number identifcation 0x39 = apds-9130 status register (0x13) the status register provides the internal status of the device. this register is read only. 7 6 5 4 3 2 1 0 status reserved psat pint reserved reserved reserved pvalid reserved 0x13 field bits description reserved 7 reserved. psat 6 proximity saturation. indicates that the proximity measurement is saturated pint 5 proximity interrupt. indicates that the device is asserting a proximity interrupt. reserved 4 reserved. reserved 3:2 reserved. pvalid 1 ps valid. indicates that the ps has completed an integration cycle. reserved 0 reserved. proximity data register (0x18 ? 0x19) proximity data is stored as a 16-bit value. to ensure the data is read correctly, a two byte read i 2 c transaction should be used with auto increment protocol bits set in the command register. with this operation, when the lower byte register is read, the upper eight bits are stored into a shadow register, which is read by a subsequent read to the upper byte. the upper register will read the correct value even if additional adc integration cycles end between the reading of the lower and upper registers. register address bits description pdatal 0x18 7:0 proximity data low byte pdatah 0x19 7:0 proximity data high byte
22 proximity ofset register (0x1e) the 8-bit proximity ofset register provides compensation for proximity ofsets caused by device variations, optical crosstalk, and other environmental factors. proximity ofset is a sign-magnitude value where the sign bit, bit 7, deter - mines if the ofset is negative (bit 7 = 0) or positive (bit 7 = 1). the magnitude of the ofset compensation depends on the proximity gain (pgain), proximity led drive strength (pdrive), and the number of proximity pulses (ppulse). because a number of environmental factors contribute to proximity ofset, this register is best suited for use in an adaptive closed- loop control system. 7 6 5 4 3 2 1 0 address poffset sign maginitude 0x1e field bits description sign 7 proximity ofset sign. the ofset sign shifts the proximity data negative when equal to 0 and positive when equal to 1. magnitude 6:0 proximity ofset magnitude. the ofset magnitude shifts the proximity data positive or negative, depending on the proximity ofset sign. the actual amount of the shift depends on the proximity gain (pgain), proximity led drive strength (pdrive), and the number of proximity pulses (ppulse).
23 apds-9130 int sda scl v d d leda 1 f v oltage regulator v oltage regulator 10 f * cap v alue per regulator manufacturer recommendation gnd v bus r p r p r p i c* 1 f ldr ledk 1 f v oltage regulator 10 f 1 f 22 apds-9130 int sda scl v d d leda gnd v bus r p r p r p i ldr ledk application information: hardware in a proximity sensing system, the included ir led can be pulsed with more than 100 ma of rapidly switching current, therefore, a few design considerations must be kept in mind to get the best performance. the key goal is to reduce the power supply noise coupled back into the device during the led pulses. averaging of multiple proximity samples is recommended to reduce the proximity noise. the frst recommendation is to use two power supplies; one for the device v dd and the other for the ir led. in many systems, there is a quiet analog supply and a noisy digital supply. by connecting the quiet supply to the v dd pin and the noisy supply to the leda pin, the key goal can be met. place a 1 f low-esr decoupling capacitor as close as possible to the v dd pin and another at the leda pin, and at least 10 f of bulk capacitance to supply the 100 ma current surge. this may be distributed as two 4.7 f capacitors. figure 12a. proximity sensing using separate power supplies if it is not possible to provide two separate power supplies, the device can be operated from a single supply. a 22 resistor in series with the v dd supply line and a 1 f low esr capacitor efectively flter any power supply noise. the previous capacitor placement considerations apply. figure 12b. proximity sensing using single power supply v bus in the above fgures refers to the i 2 c bus voltage. the i 2 c signals and the interrupt are open-drain outputs and require pull-up resistors. the pull-up resistor (r p ) value is a function of the i 2 c bus speed, the i 2 c bus voltage, and the capacitive load. a 10 k pull-up resistor (r pi ) can be used for the interrupt line.
24 package outline dimensions pcb pad layout suggested pcb pad layout guidelines for the dual flat no-lead surface mount package are shown below. notes: all linear dimensions are in mm. 0.60 0.60 0.72 (x8) 0.25 (x6) 0.80 ? 1 0.05 ? 0.90 0.05 2.40 0.05 1.34 0.58 0.05 1.18 0.05 1.35 0.20 2.36 0.2 3.94 0.2 1 2 3 4 4 3 2 1 2.10 0.1 3.73 0.1 pinout 1 - sda 2 - int 3 - ldr 4 - ledk 5 - leda 6 - gnd 7 - scl 8 - vdd 0.80 0.60 0.075 (x8) 0.05 0.05 0.25 (x6) 0.72 0.075 (x8) 5 6 7 8 5 6 7 8
25 tape dimensions all dimensions unit: mm k0 a0 b0 12 +0.30 -0.10 4 0.10 ? 1.50 0.10 1.75 0.10 2 0.05 8 0.10 5.50 0.05 ? 1 0.05 unit orientation a a 4.30 0.10 0.29 0.02 1.70 0.10 6 max 2.70 0.10 8 max reel dimensions tape width t w1 w2 w3 12mm 4+/- .50 12.4 + 2.0 - 0.0 18.4 max 11.9 min 15.4 max
26 package outline dimensions for option -140 pcb pad layout for option -140 0.80 (x8) 0.50 (x6) 0.80 (x8) 4.54 0.45 0.62 top view side view bottom view 1 2 3 4 5 6 7 8 4.94 0.20 3.36 0.20 0.50 0.20 0.50 0.20 0.50 0.20 0.50 0.20 2.80 0.20 1 2 3 4 5 6 7 8 0.120 0.075 0.120 0.075 0.200 0.075 4.54 0.10 0.45 0.10 0.80 (x8) 0.10 0.50 (x6) 0.10 0.80 (x8) 0.10 0.62 0.10
27 tape dimensions for option -140 reel dimensions for option -140 tape width t w1 w2 w3 12mm 4+/- .50 12.4 + 2.0 - 0.0 18.4 max 11.9 min 15.4 max 12 0.20 1.50 + 0.10 0 1.50 + 0.10 0 (4.00x10)=40 0.20 4 0.10 2 0.10 12 0.10 1.75 0.10 5.50 0.05 a a b b 3.62 0.10 section a-a 3 deg max 0.40 0.05 3.15 0.10 5.20 0.10 section b-b 3 deg max unit orientation
28 package outline dimensions for option -200 pcb pad layout for option -200 0.80 (x8) 0.50 (x6) 0.80 (x8) 4.54 0.45 0.62 top view side view bottom view 1 2 3 4 5 6 7 8 4.94 0.20 3.36 0.20 0.50 0.20 0.50 0.20 0.50 0.20 0.50 0.20 3.50 0.20 1 2 3 4 5 6 7 8 0.120 0.075 0.120 0.075 0.200 0.075 4.54 0.10 0.45 0.10 0.80 (x8) 0.10 0.50 (x6) 0.10 0.80 (x8) 0.10 0.62 0.10
29 tape dimensions for option -200 reel dimensions for option -200 0.40 0.05 3.85 0.10 5.20 0.10 section b-b 3 deg max unit orientation 12 0.20 1.50 + 0.10 0 1.50 + 0.10 0 (4.00x10)=40 0.20 4 0.10 2 0.10 12 0.10 1.75 0.10 5.50 0.05 a a b b 3.62 0.10 section a-a 3 deg max tape width t w1 w2 w3 12mm 4+/- .50 12.4 + 2.0 - 0.0 18.4 max 11.9 min 15.4 max
30 moisture proof packaging all apds-9130 options are shipped in moisture proof package. once opened, moisture absorption begins. this part is compliant to jedec msl 3. units in a sealed mositure-proof package package is opened (unsealed) environment less than 30 deg c, and less than 60% rh? package is opened less than 168 hours? perform recommended baking conditions no baking is necessary no yes no yes baking conditions: package temperature time in reel 60 c 48 hours in bulk 100 c 4 hours if the parts are not stored in dry conditions, they must be baked before refow to prevent damage to the parts. baking should only be done once. recommended storage conditions: storage temperature 10 c to 30 c relative humidity below 60% rh time from unsealing to soldering: after removal from the bag, the parts should be soldered within 168 hours if stored at the recommended storage conditions. if times longer than 168 hours are needed, the parts must be stored in a dry box
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2013 avago technologies. all rights reserved. av02-3425en - july 9, 2013 the refow profle is a straight-line representation of a nominal temperature profle for a convective refow solder process. the temperature profle is divided into four process zones, each with diferent ? t/ ? time tem - perature change rates or duration. the ? t/ ? time rates or duration are detailed in the above table. the temperatures are measured at the component to printed circuit board connections. in process zone p1, the pc board and component pins are heated to a temperature of 150 c to activate the fux in the solder paste. the temperature ramp up rate, r1, is limited to 3 c per second to allow for even heating of both the pc board and component pins. process zone p2 should be of sufcient time duration (100 to 180 seconds) to dry the solder paste. the temperature is raised to a level just below the liquidus point of the solder. process zone p3 is the solder refow zone. in zone p3, the temperature is quickly raised above the liquidus point of solder to 260 c (500 f) for optimum results. the dwell recommended refow profle process zone symbol ? t maximum ? t/ ? time or duration heat up p1, r1 25 c to 150 c 3 c/s solder paste dry p2, r2 150 c to 200 c 100 s to 180s solder refow p3, r3 p3, r4 200 c to 260 c 260 c to 200 c 3 c/s -6 c/s cool down p4, r5 200 c to 25 c -6 c/s time maintained above liquidus point , 217 c > 217 c 60 s to 120 s peak temperature 260 c C time within 5 c of actual peak temperature > 255 c 20 s to 40 s time 25 c to peak temperature 25 c to 260 c 8 mins time above the liquidus point of solder should be between 60 and 120 seconds. this is to assure proper coalescing of the solder paste into liquid solder and the formation of good solder connections. beyond the recommended dwell time the intermetallic growth within the solder con - nections becomes excessive, resulting in the formation of weak and unreliable connections. the temperature is then rapidly reduced to a point below the solidus temperature of the solder to allow the solder within the connections to freeze solid. process zone p4 is the cool down after solder freeze. the cool down rate, r5, from the liquidus point of the solder to 25 c (77 f) should not exceed 6 c per second maximum. this limitation is necessary to allow the pc board and component pins to change dimensions evenly, putting minimal stresses on the component. it is recommended to perform refow soldering no more than twice. 50 100 150 200 250 300 t-time (seconds) 25 80 120 150 180 200 230 255 0 temperature (c) r1 r2 r3 r4 r5 217 max 260 c p1 heat up p2 solder paste dry p3 solder reflow p4 cool down 60 sec to 120 sec above 217 c

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